The present invention relates to universal asynchronous receiver-transmitters (UARTs), and in particular to setting a delay between a last transmission and the reception of data.
UARTs are used in many communications applications to convert data streams from parallel to serial, enabling a serial data stream to communicate with a central processing unit or CPU. UARTs have increased in complexity over the years, with a single UART being able to serve multiple channels.
In operation, a typical FIFO will transmit data until its first-in, first-out (FIFO) transmit buffer is empty. It will then send a control signal indicating it is ready to receive data, the receive transmit signal (RTS). A complication that arises is that the data emptied from the buffer is shifted out onto the serial communication line via a shift register. In addition to the buffer being emptied, time must be allowed for the last word to shift through the shift register.
In addition, an amount of time must be allowed for the transmission time for the last word over the transmission line. This time can vary depending upon the length of the transmission line, its quality, the termination impedance, etc. Accordingly, most communication channels have a built-in delay which allows sufficient delay for a worst case of this combination of events. The delay is typically timed from the TxRDY signal, which is generated from the start bit of the last word. Thus, the delay is from this start bit. Even the word length can vary in some applications, thus this produces another variation in the amount of delay needed.
Some users have desired to customize their applications to shorten this delay where they know they have a short transmission line, good quality, etc. In one known embodiment, this is done by using a programmable logic array (PAL) connected on a board to the UART, with discreet resistors being used to set the delay time. The RTS signal is intercepted, delayed appropriately using the TxRDY signal, and then allowed to proceed after the delay (which is set by the external PAL circuit and discreet resistors). It would be desirable to simplify and improve the accuracy of such a programmable delay.